The present invention is directed to verifying conversion of an architecture-specific design of a first type into an architecture-specific design of a second type such that race conditions and other anomalies are detected in the second type.
Xilinx, Inc. the assignee of the present application, manufactures logic devices. Xilinx produces logic devices with either programmable interconnects (such as pass transistor interconnects) or fixed interconnects made with a mask in the metalization process. A logic device (either mask programmable or with a programmable interconnect) is an integrated circuit chip which includes a plurality of programmable input/output pads and a plurality of configurable logic elements. Each configurable logic element implements a logic function of the xe2x80x9cnxe2x80x9d inputs to the logic element according to how the logic element has been configured. Logic functions may use all n inputs to the logic element or may use only a subset thereof. A few of the possible logic functions that a logic element can be configured to implement are: AND, OR, XOR, NAND, NOR, XNOR and mixed combinations of these functions. The implementation and operation of logic devices with programmable interconnects made by Xilinx are described in xe2x80x9cThe Programmable Logic Data Book,xe2x80x9d pages 4-1 to 4-372, copyright 1996 by Xilinx, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. The contents of xe2x80x9cThe Programmable Logic Data Bookxe2x80x9d are incorporated herein by reference. Since the interconnects are programmable, and often reprogrammable, the programmable interconnect logic devices often are used to prototype a new design which may be changed in the design or debugging phase. A designer selects how signals from I/O blocks and configurable logic elements are to be routed by the programmable interconnect, thereby selecting which signal is applied to which line. The configurability of these programmable interconnect logic devices allows designers to program and test the chips locally without waiting for a mask programmable logic device or an application specific integrated circuit to be manufactured by a foundry. This enhances the designer""s productivity.
However, there are many situations where the programmable interconnect logic devices are inappropriate for the final design. For example, when high speed is critical, a mask programmable logic device would likely provide better speed than a configurable one. Further, the non-configurable device is typically cheaper to distribute commercially than its configurable counterpart. In cases such as these, it is important to provide a reliable conversion path from the configurable logic device to a non-configurable equivalent.
Xilinx provides a non-configurable (mask-programmed) hardware device called xe2x80x9cHardWirexe2x80x9d to which designs for configurable logic devices can be converted. A HardWire device uses the same logic elements placed in the same location as in a customer""s original FPGA design, only the routing architecture changes. A description of the HardWire architecture is provided in the HardWire Data Book, published by Xilinx, Inc., the contents of which are incorporated herein by reference. Chapter 2 of the HardWire Data Book is entitled xe2x80x9cFPGA Design Considerations for HardWire Designsxe2x80x9d and describes some of the issues that are involved in producing a HardWire design from a configurable logic device design. As described above, one of the major changes in using a non-configurable device is a change in speed. Propagation delays from programmable pass transistors used to implement routing in an FPGA are eliminated when pass transistors are replaced by segments in the metalization layers in HardWire. As a result, hidden race conditions latent in the design may appear when converting to HardWire. The increased speed of a HardWire part can also create new problems. Chapter 2 describes setup and hold time requirements and I/O slew rate issues. Increasing the routing speed between logic blocks decreases the amount of time that a signal is kept on a line. Accordingly, it is possible that the HardWire design will no longer meet the hold time requirements, causing errors in the operation of the device or of a system in which the device is placed. Likewise, faster routing can reduce the amount of setup time that is available after a clock pulse. The HardWire Data Book, however, does not describe how to consistently overcome these problems.
The present invention allows a design implemented in a configurable FPGA to be implemented in a non-configurable (HardWire) device without problems due to changes in timing. A reduced engineering effort is required to guarantee that conversion will produce a HardWire device that meets all timing requirements placed on the original configurable FPGA.
According to the invention, timing requirements that were made by the original designer of the configurable FPGA are combined with timing requirements determined from an analysis of critical paths in the configurable FPGA to determine timing requirements that must be met in the HardWire device.
The method of the invention first extracts parameters of the original FPGA device that are important in calculating delays in the HardWire device. These parameters are extracted from a netlist describing the customer""s original design and from a speeds file describing path delays in the original FPGA device. They include any delay requirements (maximum or minimum) placed by the customer as well as delays or critical paths determined from analysis of the customer""s design. A set of specifications is generated for use in analyzing delays in the HardWire device.
Using libraries of delays for the various HardWire devices and specific data for the particular HardWire device implementing the conversion, the method includes a timing analysis of the original design as implemented in the HardWire device, taking account of any structures that are different from those in the FPGA device, and generates a report (textual or graphic) for indicating to a user what timing problems may exist after the conversion. In one embodiment, the method includes specifying paths to which delay must be added in order to avoid race conditions that (1) were acceptable before conversion and (2) must be made acceptable after conversion.